The invention relates to processing data at data network nodes, and in particular to methods and apparatus for performing Direct Memory Access (DMA) data transfers with improved efficiency.
In the field of data processing it is known to use data buses to enable data transfers between data bus connected devices. In the field of data networking, network nodes such as, but not limited to: data switching nodes, bridges, routers, hubs, aggregation devices, deaggregation devices, multiplexers, demultiplexers, etc. are computing platforms which include data bus connected devices such as: memory storage, processors, physical interface peripherals (cards), etc.
Typical network node designs have an architecture in which a single bus master, a Central Processing Unit (CPU), oversees and coordinates the overall operation thereof. For short periods of time, as directed by the CPU, other data bus connected devices may control the data bus through bus mastering techniques.
Recently data network node designs have an architecture in which multiple data bus connected devices, such as processors and physical interface peripherals, cooperate to access a central memory storage to process data, each such data bus connected device operating as a bus master.
Although network nodes can be implemented on a computing platform such as a ubiquitous microcomputer, high data throughput capacity high performance network nodes are implemented as special purpose data processing equipment.
Data is received and transmitted via a multitude of interconnecting links associated with physical interfaces on the network equipment. In processing data at network nodes, data is received, switched and transmitted either severally or in combination in accordance with a multitude of transfer protocols. Each combination of a transfer protocol and a physical interface conveys data having a data format. The data format specifies a data transfer order and an alignment. Furthermore the data bus connected devices such as: interface cards, memory blocks, mass storage devices, switching processors, functional processors, supervisory processors, etc. process and convey data in accordance to a data transfer order and alignment associated therewith. Due to a competitive rapid development of data transport equipment and transport protocols, a data transfer order and alignment mismatch may exist therebetween.
A variety of data ordering conventions are being used and relate to an order in which data bits constitutive of data bytes are received, processed and transmitted. Data bit ordering includes, but is not limited to: a little-endian bit order and a big-endian bit order. With the advent of wide data buses the data ordering also includes byte ordering. A byte is a unit of data comprised of a sequence of bits used to represent numerical values and typographical symbols such as: characters and decimals. Data byte ordering includes, but is not limited to: a little-endian byte order and a big-endian byte order. Bytes are used singly or in combination to specify numerical values representative of the data. Combinations of two bytes are referred to as words, whereas combinations of four bytes are referred to as double words or dwords.
Little-endian ordering refers to the conveyance and/or processing of Least Significant Bits (LSB) of bit streams or bytes, first. With respect to bytes, little-endian ordering refers to the conveyance and/or processing of Least Significant Bytes (LSB) of a word/dword, first. Big-endian ordering refers to the conveyance and/or processing of Most Significant Bits/Bytes (MSB) first.
Bytes may be ordered in a variety of ways, the ordering being a design choice and/or a necessity in efficiently conveying and/or processing data for a particular application such as a network node.
The conveyance of data over data links (including between dissimilar vendor equipment) is also subject to data ordering imposed by transfer protocols used. Therefore, there may exist a clash between a network node implementing a particular byte order used in processing the data, such as little-endian byte ordering, whereas the transfer protocol used specifies a different byte order used in conveying data, such as big-endian byte ordering. The clash can only be eliminated by reordering the bytes at the network node prior to transmission or post reception of data.
The recent explosion of technological advances in the telecommunications field has benefited from a competitive environment in which a relatively large number of vendors have produced and deployed a large number of network node models using a large number of interface types each of which adhering to at least one of a relatively large number of transfer protocols.
Another important factor to be considered in processing data concerns data alignment and in particular byte alignment. The data buses used in conveying data internally between data bus connected devices use parallel data transfers, with 2, 4, 8, 16, etc. bytes being transferred on each cycle of an associated data bus clock according to the data bus width. For example, 4 bytes of data are transferred on each clock cycle for a 32 bit data bus.
Data buses also make use of addressing lines, integral to each data bus, to select memory locations where to write to, and to read from. Although indirect addressing is used to access every byte of data in memory, it is common practice to address a number of bytes at the same time since the bytes are transferred over the data bus in groups. For the above example, typically when using a 32 bit data bus, data bus addressing locations are defined every 4 bytes. This is referred to as dword alignment of data. Indirect addressing of data, to access the individual bytes in each dword for example, is performed subsequent to the transfer of the dword from the memory for processing. A data processing overhead is incurred if only a fewer number of bytes from the transferred dword are used in processing.
Such overheads can be significant in data switching environments where the data to be processed includes Protocol Data Units (PDUs). Each PDU has a PDU header and a payload. The header specifies routing information in accordance with a particular transfer protocol and is updated or rewritten at each network node in a transport path. The header may be discarded altogether as the data conveyed undergoes protocol conversion. The header may be considered part of the payload as the PDU is encapsulated and conveyed using another transfer protocol. All these processes necessitate data re-alignment in the processing thereof.
Prior art data bus connected devices such as interface cards, mass storage devices, etc. rely on switching processors, functional processors, supervisory processors, etc. to provide correct data ordering and alignment. Depending on the byte order of the data processing equipment and the applications used, a processor takes the time-consuming job to re-organize and re-order the data using storage resources and processing cycles to copy the data, re-order the bytes, and re-align the bytes before and/or after processing.
Current network nodes support a variety of low capacity and high capacity interfaces as well as a variety of transfer protocols to provide aggregation/deaggregation functionality in addition to PDU switching therefore a significant amount of processing time is devoted to reordering and re-aligning data.
An attempt at relieving a CPU from performing byte re-ordering is presented in prior art U.S. Pat. No. 5,862,407 entitled xe2x80x9cSYSTEM FOR PERFORMING DMA BYTE SWAPPING WITHIN EACH DATA ELEMENT IN ACCORDANCE TO SWAPPING INDICATION BITS WITHIN A DMA COMMANDxe2x80x9d which issued on Jan. 19th, 1999 to Sriti describes a video card for a computer which conveys a data stream using multiplexers. Based on swapping indication bits, the video card uses a different multiplexer tap for read and/or write operations. Although inventive, the swapping indication bits are specified by a high level software application such as a video driver. The video driver comprises data code executed by the CPU. The swapping indication bits are stored along with a data transfer length specification trading off the ability of the data transfer length specifierxe2x80x94the data transfer length specifier being only able to specify the data transfer lengths in terms of double words.
Due to strict data processing requirements in PDU switching environments, software involvement in the byte ordering specification introduces unwanted inefficiencies if used. The methods provided by the prior art further assume a double word alignment of data at all times. However, without the ability of specifying data transfer lengths in bytes, the prior art methods do not provide a suitable solution for byte level data transfers except through processing intensive indirect addressing. Furthermore the data needs to be aligned during data transfers since the assumption of double word aligned data cannot be relied upon.
There therefore is a need to provide methods and apparatus to overcome the above mentioned issues in providing efficient data transfers in processing data.
In accordance with an aspect of the invention, a network node processing Protocol Data Units (PDUs) is provided. The network node includes: a central memory store for retrievably storing PDU data segments, a byte order specification register specifying a byte order for data stored in the central memory store, and at least one peripheral interface conveying PDU data having a byte order. Each peripheral interface includes: a byte order specification register specifying the byte order of the PDU data conveyed a data channel, and a direct memory access controller. The direct memory access controller is responsive to byte order specifications in conveying data. The direct memory access controller performs byte order conversion on the data during the conveyance thereof reducing processing overheads at the network node.
In accordance with another aspect of the invention, a peripheral interface conveying PDU data via a channel is provided. The peripheral interface has a channel byte order specification register specifying a byte order of the PDU data conveyed via the data channel. The peripheral interface also has a direct memory access controller responsive to a system byte order specification register and the channel byte order register to perform byte order conversion on the PDU data during the conveyance thereof at reduced processing overheads.
In accordance with a further aspect of the invention, a direct memory access descriptor specification is provided. The direct memory access descriptor tracks data segment information and includes: a direct memory access descriptor address specifier, a data structure delimiter specifier, a start memory storage address specifier, a data size specifier, and a byte order specifier. The DMA descriptor address specifier points to a next direct memory address descriptor. The start memory storage address specifier points to a memory segment. And, the data size specifier holds a number of contiguous data bytes stored in the memory segment.
In accordance with yet another aspect of the invention, a state machine specifying values of an orphan counter is provided. The orphan counter is used for gathering, re-ordering and aligning data conveyed.
The advantages are derived from a reduction in processing overheads associated with byte gathering, byte reordering and aligning data.